Job listing
Lead Physical Design Engineer
Astera Labs
- Bangalore, Karnataka, India
- Onsite, Full Time
Skills
- Cadence
- Synopsys
- Synthesis tools
- Place and Route
- CTS
- STA
- Physical Verification
- DFT tools
- SystemVerilog
- Verilog
- Python
- Perl
- GDSII
- IP vendors
About the role
6+ YOE6-10 years in SoC/silicon backend, synthesis, place and route, CTS, extraction/STA, PVT, DFT; Cadence/Synopsys tools; SystemVerilog/Verilog; IP vendor collaboration; Python/Perl scripting.